After all processes are carried out, semiconductor devices are packaged and their functions are electrically tested by means of a tester and handler. The tester, which includes a waveform generator, a current/voltage generator, and a current/voltage-measuring unit, tests the electrical functions of semiconductor devices according to the test program. The handler is a kind of robot that automatically conducts the electrical function test for each semiconductor “device under test” (DUT). The handler is an automated assembly to load/unload the DUTs for testing and to sort the tested DUTs based on the test result. A test station is a place where the tester conducts the electric function test, and a test head is a kind of a gate between the handler and the tester.
A test flow between a tester and a handler head is described below with reference to FIG. 1.
Referring to FIG. 1, a signal is transmitted between a handler head 100 and a tester 120 through a communication interface 130. While chips are moved from the chip tray to the handler head 110, the tester 120 is in an idle state ({circle around (1)}). When a chip is connected to a socket, the handler head 110 transmits a test-start signal to the tester 120 ({circle around (2)}). The tester 120 tests the electronic function of the chip in response to the test-start signal and transmits a test-end signal to the handler head 110 when the test ends ({circle around (3)}). The handler head 110 sorts the tested chips into good chips and defective chips ({circle around (4)}). At this time, the tester is again in the idle state. A reduction or elimination of the tester idle time is desirable because it would improve the efficiency of the test apparatus.
One example of a test apparatus that reduces tester idle time is disclosed in Korean Patent Application No. 2000-56000, in which a multi-handler has two test points, two sorting means, and two loading lanes, and a test signal is transmitted in a time-division manner to each of the alternate paths of the multi-handler. A test apparatus according to the above patent includes two handlers, two stations, and two head boards. While one semiconductor device is tested at one handler portion, another semiconductor device is sorted and a new semiconductor device is loaded at another handler portion. Unfortunately, because so many of the handler components are duplicated, the test apparatus of the above patent is still fairly large.